Silicon substrates used as semiconductor device substrates such as memories, logics, and solid-state image sensors are cut from silicon single crystal ingots produced by the Czochralski (CZ) method or other methods. There is an increasing need for various wafers produced depending on use: polished wafers obtained from silicon substrates subjected to mirror polishing; annealed wafers obtained from the polished wafers subjected to an annealing process to suppress defects in their surface layer or to form an intrinsic gettering (IG) layer in their bulk; epitaxial wafers each having a formed epitaxial layer; and SOI wafers. Silicon substrates containing oxygen atoms are used in an attempt to increase IG capability so that higher performance devices with higher reliability are obtained.
It is known that these oxygen atoms contained in the silicon substrates are combined with silicon atoms by a heat treatment process to form oxide precipitates and bulk micro defects (BMDs), which capture contaminant atoms such as heavy metal atoms in the interior of the wafers, thereby improving device characteristics.
In recent years, sufficient IG capability is given by control of single crystal so as to take in oxygen at a high concentration or production involving intentional doping of carbon or nitrogen, while crystal defects in the silicon substrate is regulated. In particular, a solid-state image sensor uses an epitaxial wafer obtained by forming an epitaxial layer on a silicon substrate cut from a silicon single crystal ingot produced in this way.
This epitaxial wafer has a rational structure that can separate the epitaxial layer, which is a region at which a device is to be formed, from the silicon substrate. Making use of this feature, there are many suggestions to give sufficient IG capability to the silicon substrate, which is not the region at which a device is to be formed.
One of these recently used is to produce a silicon substrate by growing a silicon single crystal ingot doped with elements such as nitrogen or carbon by the CZ method and slicing this ingot. This enables the silicon substrate to precipitate oxygen remarkably in its bulk and form BMD at a high density in a device process. Such a substrate has a wider range of uses because of an advantage in its excellent IG capability.
An epitaxial wafer as shown in FIG. 3 is also used for a device. FIG. 3 is a schematic diagram of a conventional silicon epitaxial wafer. This wafer has an intermediate epitaxial layer 20 doped with p-type or n-type elements (a dopant) between a silicon substrate 10 doped with carbon and an epitaxial layer 30 of the region at which a device is to be formed.
In exemplary production of this silicon epitaxial wafer, if the intermediate epitaxial layer 20 of n+(P) is grown on the silicon substrate 10, a dopant is added by a gas dopant such that a dopant concentration is the order of 1×1016 to 1×1017 atoms/cm3 to grow the intermediate epitaxial layer 20.
The epitaxial layer 30 of the device forming region is grown after the formation of the intermediate epitaxial layer 20. In an exemplary case of growing the epitaxial layer 30 of the device forming region of n− (P), a dopant is added by a gas dopant such that a dopant concentration is the order of 1×1013 to 1×1015 atoms/cm3 to grow the epitaxial layer 30 of the device forming region.
In this manner, these processes of epitaxial growth enable acquisition of a silicon epitaxial wafer having a two-layer structure of epitaxial layers that can be expressed by n− (substrate)/n+/n−. This epitaxial wafer having a two-layer structure have various uses. The epitaxial layer 30 is not only the device forming region but also a region at which a well is formed. As shown in FIG. 4, for example, p-type impurities may be implanted selectively into the epitaxial layer 30 (n−) of the device forming region to form a p-type conductive layer 30p after the n− (substrate)/n+/n− silicon epitaxial wafer has been obtained. In this case, there is a p/n boundary in a boundary region between the p-type conductive layer 30p and the intermediate epitaxial layer 20 (n+).
The distance between a surface of a wafer and this p/n boundary is important in designing devices. As the shrinking of devices recently advances, an error of the order of micrometers or submicrometers of this distance becomes a potential factor in impeding electrical characteristics. For a solid-state image sensor, for example, such an error is an obstacle to transfer of part of an electric charge accumulated in a photodiode to the epitaxial layer 30 (n−) of the device forming region. The position of the p/n boundary between the epitaxial layer 30 (n−) of the device forming region and the p-type conductive layer 30p is accordingly important. Nonuniform distance between the p/n boundary and the wafer surface can cause an uneven image of the solid-state image sensor.
The position of the p/n boundary is determined by a distance at which elements in the intermediate epitaxial layer (n-type elements, here) are diffused by a thermal process in a device process. Thus, this diffusion distance of elements in the intermediate epitaxial layer 20 (n-type elements, here) subjected to the thermal process is also a control factor that has considerable influence.
For example, Patent Document 1 discloses definition of the thickness of a device forming region formed on a silicon substrate produced from a CZ silicon single crystal ingot doped with carbon.
In recent years, however, the device forming region is required to have a decreased thickness while the shrinking of devices advances as described above. There is a need to suggest a wafer that does not impede device characteristics even when the thickness of its device forming region is thin, especially in order to make the best use of the advantage of the CZ silicon substrate doped with carbon having excellent IG capability.